Conventional methods of fabricating integrated circuit devices may utilize metal damascene process steps to define multi-layer metal interconnects on a semiconductor substrate. As illustrated by FIGS. 1A-1C, one conventional method may include forming a first electrically insulating layer 14 on a semiconductor substrate 10 having trench isolation regions 12 therein. This first electrically insulating layer 14 may be formed directly on a surface of the substrate 10 in order to provide a degree of passivation for underlying device structures (e.g., gate electrodes 13). The first electrically insulating layer 14 may be photolithographically patterned to define a plurality of contact holes 15 therein. As illustrated, the density of the contact holes 15 may vary with location on the substrate 10. After formation of the contact holes 15, a blanket layer 16 of a first electrically conductive material (e.g., tungsten (W)) may be conformally deposited on the first electrically insulating layer 14.
As illustrated by FIG. 1B, this blanket layer 16 may be planarized for a sufficient duration to expose the first electrically insulating layer 14 and thereby define a first plurality of conductive vias 16a, 16b and 16c. This planarization step may be performed as a conventional chemical-mechanical polishing (CMP) step using a polishing apparatus in combination with a slurry solution that is applied to an upper surface of the blanket layer 16 during polishing. Unfortunately, during polishing, a “dishing” phenomenon may result in an excessive recession of the first electrically insulating layer 14 opposite those portions of the substrate 10 containing a relatively high density of conductive vias 16c. Thereafter, as illustrated by FIG. 1C, a second electrically insulating layer 18 may be deposited on the structure of FIG. 1B and then patterned to define openings therein that are aligned with the conductive vias 16a, 16b and 16c. Next, a blanket layer of a second electrically conductive material (e.g., copper (Cu) or tungsten (W)) may be conformally deposited on the second electrically insulating layer 18. This blanket layer may then be planarized using CMP to define a second plurality of metal lines 20a, 20b, 20c and 20d. Unfortunately, because of the excessive recession of the first electrically insulating layer 14 illustrated by FIG. 1B, the planarization of the second electrically conductive material may result in the formation of a relatively wide metal line 20d that electrically shorts adjacent conductive vias 16c together. This relatively wide metal line 20d represents a metal defect (e.g., metal line short) that may significantly reduce device yield after back-end processing steps have been completed.